1. Field of the Invention
The present invention relates to an input buffer, and in particular to an input buffer providing substantially the same signal transition time from high to low as from low to high.
2. Description of the Related Art
Transistor-transistor-logic (TTL) operating characteristics are well known in the art. For example, a TTL low signal is typically any voltage under 0.8 volts, whereas a TTL high signal is typically any voltage over 2.0 volts, and the threshold voltage is about 1.5 volts. In many digital signal applications, CMOS devices require TTL compatible input buffers.
FIG. 1 illustrates a conventional TTL/CMOS input buffer 100 which includes two inverters 105A and 105B. Inverter 105A includes a p-type transistor 103 and an n-type transistor 104. If a low signal is provided at input terminal 101, this low signal turns on transistor 103, and turns off transistor 104. Because transistor 103 is on, a high signal, provided by voltage source Vcc, is transferred to node A. In contrast, if a high signal is provided at input terminal 101, this high signal turns on transistor 104, and turns off transistor 103. Because transistor 104 is on, this transistor pulls down the voltage on node A to ground. Inverter 105B has a similar configuration to inverter 105A and therefore is not described in detail. Thus, a high signal on input terminal 101 results in a high signal on output terminal 102.
To ensure buffer 100 exhibits a TTL 1.5 V threshold voltage, n-type transistor 104 is sized larger than p-type transistor 103. In fact, transistor 104 typically has a width (Wn) approximately four or five times greater than the width (Wp) of transistor 103 (assuming transistors 104 and 103 have the same channel length). For example, in one embodiment of buffer 100, transistor 104 has a width of 150 microns while transistor 103 has a width of 30 microns. However, this large width differential creates an imbalanced switching delay from input terminal 101 of inverter 105A to node A. Specifically, the high to low signal transition of inverter 105A (as measured at node A) is much faster than the signal transition from low to high. For example, in the embodiment shown in FIG. 1, the switching delay beginning when a signal at input terminal 101 switches from high to low and ending when the signal at node A switches from low to high is about 1.05 nanoseconds. In contrast, the switching delay beginning when a signal at input terminal 101 switches from low to high and ending when the signal at node A switches from high to low is about 440 picoseconds. Thus, a device time delay specification which includes input buffer 100 varies depending on signal transition. This variation in device time delay is highly undesirable because end users require a consistent time delay specification for application use.
To solve this problem, buffer 100 uses inverter 105B which is cascaded with inverter 105A to balance out the skew created by inverter 105A. Inverter 105B includes a p-type transistor 106 having a width of 30 microns and an n-type transistor 107 having a width of 45 microns. Because transistor 107 is slightly wider than transistor 106, transistor 107 is slightly stronger than transistor 106. Therefore, in a low to high signal transition at node A, transistor 107 accelerates pulling down the voltage provided at output terminal 102, thereby substantially compensating for the slower pull-up provided by transistor 103.
However, this solution generates an overall switching delay from input terminal 101 to output terminal 102 which is highly undesirable for many CMOS applications. Therefore, a need arises for a buffer which equalizes switching delays while at the same time minimizing the time delay between the input terminal and the output terminal.